EDN

Illogical Logic Part 3 – D-Type Flip-Flops

When it comes to illogical logic circuits I have to say I was always scratching my head when it came to Edge Triggered D-Type Flip-Flops. These are one of the most common logic blocks in today’s ...
EDN

How to Read Data Sheets: Logic Timing (Part 3, Flip-Flops)

The JK flip-flop augments the behavior of the SR flip-flop (J = Set, K = Reset) by interpreting the J = K = 1 condition as a “flip” or toggle command. In my previous column, we introduced latches and ...
Hackaday

Pipelining Digital Logic In FPGAs

When you first learn about digital logic, it probably seems like it is easy. You learn about AND and OR gates and figure that’s not very hard. However, going from a few basic gates to something like a ...
TechRepublic

Implementing Efficient Embedded Logic in Low Power Twin Dynamic Pulsed Hybrid Flip-Flop

Flip flops are critical timing elements in digital circuits which have large impact on circuit speed and power consumption. The parameters to be considered while designing a flip flop is power and ...
Embedded

Leveraging FPGA and CPLD digital logic to implement analog to digital converters

Designers of digital systems are familiar with implementing the 'leftovers' of their digital design by using FPGAs and CPLDs to glue together various processors, memories, and standard function ...