Design-Reuse

Low Power Design Methodology for Core based ASSP

As the design cycles are shrinking and complexity is increasing by many folds, it has become a regular practice to develop the Application Specific Standard Products (ASSP) by using readily available ...
Design-Reuse

Low power vlsi circuits IP Listing

The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication factors up to 8192, allowing the PLL to ... The DB ...
Drexel University

Scott Lerner

Scott Lerner is a PhD student in Electrical Engineering. His research interests include low-power VLSI circuits, modeling of parametric variation, and timing models specifically for clock distribution ...
Electronic Design

Understanding Low-Power IC Design Techniques

Low-power IC design techniques have been around for quite a while. They weren’t always required, though they were nice to have. The rapid growth of the consumer market for battery-powered devices has ...
EDN

VLSI papers weigh 65 nm, new circuits

AUSTIN, Texas — While technologists look to 65-nanometer nodes, circuit designers by and large are two generations back. So it's no surprise that as a string of 65-nm papers are delivered at the 2004 ...