As a digital design or verification engineer you know that certain features or configurations of the device can be achieved by programming some registers to set values. For example, a 32-bit register ...

Aldec, a specialist in verification of FPGA and ASIC designs, has added VHDL-2019 feature support and a UVM Registers window to Riviera-PRO, its high performance simulation and debugging tool. The ...

When I was preparing for a customer presentation on UVM RAL, I could not understand what the UVM base class library is saying about updating the values of desired value and the mirror value registers.

My company, TVS, recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless ...