IEEE

Design and Implementation of 32-bit RISC-V Processor Using Verilog

Abstract: The design and implementation of a 32-bit single-cycle RISC-V processor in Verilog is a sophisticated and elaborate process that aims to create a functioning processor architecture that ...
IEEE

Implementing a Secure Boot System on a 32-Bit RISC-V CPU on FPGA

Abstract: This work presents an implementation of system-on-chip (SoC), integrating a secure boot procedure based on a 32-bit RISC-V architecture CPU and hardware-accelerated cryptographic cores on an ...